1. Field of the Invention
This invention is related to semiconductor integrated circuit devices and a manufacturing technique therefor and, in particular, to a method of attaining high integration, high reliability and high performance of a nonvolatile semiconductor memory device.
2. Description of Related Art
Since flash memory devices functioning similarly to EEPROMs (Electrically Erasable Programmable Read Only Memory) are capable of electrical writing and erasing and are very portable and impact resistant, the demand therefor has recently increased rapidly for use in mobile phones, portable personal computers, digital cameras and in microcomputers in the engine control systems of automobiles.
To improve the marketability of such devices, reduction of the memory cell area is essential for reducing the cost thereof and various memory cell systems have been proposed for attaining the same. One such system is a virtual ground type memory cell using a 3-layered polysilicon gate as disclosed, for example, in JP-A No. 200242/1999.
The memory cell of the type described above comprises, as shown in FIG. 60, a well 601 in a silicon substrate 600, source and drain diffusion layer regions 605, 605′ in the well, and three gates including a floating gate 603b as a first gate comprising a polysilicon film formed on the well, a control gate 611a as a second gate, and a third gate 607a for controlling an erasing gate and a split channel.
Each of the gates 603b, 611a, and 607a comprises a polysilicon film, and are isolated from the well 601 by insulator films 602, 606a, 606b, 608a, and 610. The control gates 611a are connected in a row to constitute word lines. The source and drain diffusion layer 605 is a virtual ground type having the diffusion layer of an adjacent memory cell in common to reduce the pitch in the direction of the row. The third gates 607a are disposed in parallel with the channels and perpendicular to the word lines 611a. 
Upon writing, positive voltage independent of each other is applied to the word line 611a, the drain 605 and the third gate 607a while setting the well 601 and the source 605′ to 0 V. Thus, hot electrons are generated in a channel at the boundary between the third gate and the floating gate and they are injected into the floating gate 603b. This increases the threshold voltage of the memory cell. Upon erasing, a positive voltage is applied to the third gate 607a while setting the word line 611a, the source 605′, the drain 605 and the well 601 to 0 V. This discharges electrons from the floating gate 603b to the third gate 607a to lower the threshold voltage. “0” and “1” of information is determined by changing the threshold voltage of the memory cell transistor.
Problems arise, however, when to the density is increased in the nonvolatile semiconductor memory device described above.
At first, this concerns the reduction in the size of the memory cell. When it is intended to further reduce the size of the split gate type memory cell, it is important to reduce the gate length for the floating gate 603b and the third gate 607a. For this purpose, it is necessary to reduce the thickness of the gate insulator films 602 and 606a and improve the punch through resistance. However, no discussion has been made on the thickness of each gate insulator film.
Next, there is a problem in improving the reliability. In a flash memory, it has to be ensured that the data is held for more than 10 years after conducting writing/erasing cycles for 100,000 cycles or more. Elimination of data is caused by leakage of electrons accumulated in the floating gate.
While there are present plural modes for the cause of the leakage, the present inventors have found that the mode where electrons accumulate in the floating gate and incidentally leak at certain bits is most problematic. Such leakage has a correlation with the thickness of the gate insulator film 602 between the floating gate and the substrate, the so-called tunnel film, and the number of failure bits increases as the thickness of film is reduced.
According to the study made by the present inventors, it is necessary to increase the film thickness of the tunnel insulator film 602 to 9 nm or more in order to hold the data for 10 years, particularly in multi-level storage of 2 bits in one memory cell. Accordingly, to minimize the size of these memory devices, the thickness of the gate insulator films 602 and 606a must be considered.
The third problem is the increase in the number of manufacturing steps. A usual flash memory has a peripheral circuit for applying voltage to the memory cell or conducting logic operations. In the circuit for applying the voltage to the cell, since a high voltage, for example, of 18 V is applied to the word line, a MOS (Metal Oxide Semiconductor) transistor constituting the circuit has a high voltage withstanding structure using a thick gate insulator film of, for example, 25 nm. On the other hand, in the circuit for conducting the logic operation, the applied voltage is, for example, 3 V of an external power source voltage and high-speed operation is required. Therefore, the thickness of the gate insulator film of the MOS constituting the circuit for conducting the logic operation is extremely thin compared with the structure for withstanding high voltage. Thus, improved manufacturing methods are needed to form the two kinds of gate insulator films for the peripheral circuit and the two kinds of gate insulator films for the memory cell to simplify production and reduce the cost thereof.
As described above, the development of a new nonvolatile semiconductor memory device and a manufacturing method therefor are desirable with respect to gate insulator films of a split gate type memory cell.
A nonvolatile semiconductor memory device of reduced size and improved reliability are desirable.
Simplified production steps for producing such nonvolatile semiconductor memory devices are also desirable.